This application is related to Japanese Patent Application Nos. Hei 9-54877 filed on Mar. 10, 1997 and Hei 10-36323 filed on Feb. 18, 1998, incorporated herein by reference.
1. Field of the Invention
The present invention relates to an MIS transistor having a so-called salicide structure in which high melting point metallic silicide film is formed on the respective upper surfaces of a gate electrode, a source and a drain, and to a fabricating method thereof.
2. Description of Related Art
A salicide structure in which a metal silicide film is formed on the respective upper surfaces of a gate electrode, a source and a drain in an MIS transistor is well known in the art. The MIS transistor having the salicide structure is formed by selectively silicifying a metal film in a region closely in contact with silicon by attaching and treating by heat the metal film while exposing the upper face of the gate electrode and the upper faces of diffusion layers of a source and a drain and by removing, by etching, the part of the metal film not treated. Subsequently, the gate electrode is electrically separated from the source and the drain by forming side wall silicon oxide (SiO2) films on the sides of the gate electrode. For the side wall oxide films, a mask (spacer) used in implanting ions to form the high concentrate source and drain having an LDD structure is utilized. However, in implanting ions, the spacer damages the bond of SiO2 composing the sidewall oxide film such that the bond is destroyed. When a salicide forming step is performed by using the damaged side wall oxide film as a mask, silicon from the damaged SiO2 reacts with the metal for forming the metal silicide film. As a result, the gate electrode often cannot be fully separated electrically from the source and the drain because the metal silicide film remains on the side wall oxide films.
Taking this problem into consideration, a method for fully separating the gate electrode from the source and the drain has been disclosed in Japanese Patent Application Laid-Open No. Hei. 4-196442.
The above application discloses that an oxide film is formed by means of CVD on the whole upper surface of a wafer after forming a gate electrode on a substrate while interposing a gate insulating film therebetween. Then, the oxide film is etched by means of RIE and is thermally oxidized to form a side wall oxide film composed of SiO2. Then, a source and a drain are formed by implanting ions by using the sidewall oxide film as a mask. After that, a part of the side wall oxide film, i.e. the part where the bond of silicon and oxygen is destroyed by the implantation of ions (hereinafter referred to as a damaged layer) is removed by wet etching. Then, a side wall oxide film is formed again on the side face of the gate electrode by the same method. After that, a titanium film is formed on the whole surface of the wafer and a heat treatment is performed to form titanium silicide films on the respective surfaces of the gate electrode, the source and the drain. Thus, an MIS transistor having the salicide structure in which the titanium silicide films are formed on the respective surfaces of the gate electrode, the source and the drain is formed.
However, the wet etching process used to remove the damaged side wall oxide film is difficult to control, and thus the thickness of the side wall oxide film varies considerably. Because the atomic structure of the damaged layer is not uniform, the variation of the degree of etching becomes significant.
The large variation in etching of the above wet etching process is also a factor causing variation in the thickness of the sidewall oxide film. Because a relatively long over-etching time is required to remove the damaged layer, the thickness of the side wall oxide film is largely influenced by the variation of the etching rate.
Due to the variation of the side wall oxide film caused by the above factors, the distance between the titanium silicide film and the PN junction at the channel region of the source and the drain varies, and often causes a leak current.
Further, the above-mentioned method is also inefficient, in that the number of steps required to fabricate the transistor is increased due to the additional step of removing the damaged layer.
Accordingly, it is a primary object of the present invention to solve the aforementioned problems by providing a method for fabricating an MIS transistor having a salicide structure that does not cause a leak current and that does not require removal of a damaged silicon oxide layer.
It is another object of the present invention to provide an MIS transistor having a salicide structure in which the variation of the distance between the metal silicide film and the PN junction at the source and the drain is small and being formed in a manner that minimizes the probability of a leak current occurring.
In order to attain the above-mentioned objects, an inventive method for fabricating an MIS transistor comprises steps of forming a gate electrode on a silicon substrate while interposing a gate insulating film therebetween; forming a thermal oxide film on the side face of the gate electrode; implanting ions by masking with the thermal oxide film to form a source and a drain; and after forming a deposited insulating film on the surface of the thermal oxide film, forming metal silicide films on the respective surfaces of the gate electrode, the source and the drain.
Because the deposited insulating film is formed after implanting ions to form the source and drain layers, the deposited insulating film is not damaged during the implanting of ions. Therefore, no metal silicide film is formed on the deposited insulating film and no metal silicide film is left on the deposited insulating film even if metal for forming the metal silicide film is placed on the deposited insulating film. Accordingly, the gate electrode, the source and the drain may be electrically separated completely.
Further, because the thermal oxide film whose thickness varies less is used as the mask in forming the source and the drain, the variation of the respective positions of the source and the drain may be reduced and the variation of the characteristic for preventing a leak current may be reduced.
It is noted that the deposited insulating film may be formed by SiO2, SiNx or the like.
Further, an impurity layer for lowering a contact resistance may be formed selectively in a predetermined region of the source and the drain. In this case, however, it is desirable to lower the resistance of the metal silicide film and to activate the impurity layer by heat treatment.
Specifically, in heat treating the metal silicide film to activate the impurity layer for lowering the contact resistance, it is preferable to avoid the heat treatment after forming the metal silicide film as much as possible to avoid the coagulation of the metal silicide film. Accordingly, it is possible to avoid a heat treatment which might induce the coagulation of the metal silicide film by performing the heat treatment for activating (diffusing) the impurity layer at the same time of forming the impurity layer to lower the resistance of the metal silicide film.
Further, it is possible to diffuse the impurity layer and simultaneously lower the resistance of the metal silicide film by forming the impurity layer after forming the metal silicide film.
Further, in addition to the source and the drain, it is possible to form a field relaxation layer by implanting ions obliquely by masking with the thermal oxide film. Because the field relaxation layer is formed by using the same mask as that used for forming the source and the drain, and the mask is the thermal oxide film whose thickness varies less, the variation of the position where the field relaxation layer is formed may be reduced.
An inventive MIS transistor comprises a gate electrode formed on a silicon substrate with a gate insulating film interposed therebetween, a thermal oxide film formed on the side face of the gate electrode, a source and a drain formed by masking with the thermal oxide film, a deposited insulating film formed on the surface of the thermal oxide film at the side wall of the gate electrode, and metal silicide films formed on the respective surfaces of the gate electrode, the source and the drain by masking with the deposited insulating film.
The positions of the source and the drain formed by masking with the thermal oxide film vary less. Further, because the metal silicide films are formed by masking with the deposited insulating film, a distance between the side edge of the channel region of the source and the drain and the metal silicide film is larger than the thickness of the deposited insulating film.
Therefore, it is possible to prevent a leak current from being generated from the metal silicide films to the channel region of the source and the drain even if the metal silicide films diffuse in the surface direction of the silicon substrate.
It is noted that it is possible to form the source and the drain by forming the gate electrode on the silicon substrate while interposing the gate insulating film therebetween and by implanting ions by masking with the gate electrode. In this case, the deposited insulating film is formed on the side wall of the gate electrode and the metal silicide films are formed on the respective surfaces of the gate electrode, the source and the drain.
Thus, the source and the drain may be formed by masking with the gate electrode.
The above and other related objects and features of the invention will be apparent from a reading of the following description of the disclosure found in the accompanying drawings and the novelty thereof pointed out in the appended claims.